13.2 x86 AND ARM ADDRESSING MODES
13.2.A x86 Addressing Modes
Recall
from Figure 8.21 that the x86 address translation mechanism produces an
address, called a virtual or effective address, that is an offset into a
segment. The sum of the starting address of the segment and the
effective address produces a linear address. If paging is being used,
this linear address must pass through a pagetranslation mechanism to
produce a physical address. In what follows, we ignore this last step
because it is transparent to the instruction set and to the programmer.
The
x86 is equipped with a variety of addressing modes intended to allow
the efficient execution of high-level languages. Figure 13.2 indicates
the logic involved. The segment register determines the segment that is
the subject of the reference. There are six segment registers; the one
being used for a particular reference depends on the context of
execution and the instruction. Each segment register holds an index into the segment descriptor table (Figure 8.20), which
holds the starting address of the corresponding segments. Associated
with each user-visible segment register is a segment descriptor register
(not programmer visible), which records the access rights for the
segment as well as the starting address and limit (length) of the
segment. In addition, there are two registers that may be used in
constructing an address: the base register and the index register.
Table
13.2 lists the x86 addressing modes. Let us consider each of these in
turn.For the immediate mode, the operand is included in the instruction.
The operand can be a byte, word, or doubleword of data.
For register operand mode, the operand is located in a register. For general instructions, such as data transfer, arithmetic, and logical instructions, the operand can be one of the 32-bit general registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP,EBP), one of the 16-bit general registers (AX, BX, CX, DX, SI, DI, SP, BP), or one of the 8-bit general registers (AH, BH, CH, DH, AL, BL, CL, DL). There are also some instructions that reference the segment selector registers (CS, DS, ES, SS, FS, GS).
The remaining addressing modes reference locations in memory. The memory location must be specified in terms of the segment containing the location and the offset from the beginning of the segment. In some cases, a segment is specified explicitly; in others, the segment is specified by simple rules that assign a segment by default.
In the displacement mode, the operand’s offset (the effective address of Figure13.2) is contained as part of the instruction as an 8-, 16-, or 32-bit displacement.With segmentation, all addresses in instructions refer merely to an offset in a segment. The displacement addressing mode is found on few machines
because, as mentioned earlier, it leads to long instructions. In the case of the x86,
LA = linear address
(X) = contents of X
SR = segment register
PC = program counter
A = contents of an address field in the instruction
R = register
B = base register
I = index register
S = scaling factor
the displacement value can be as long as 32 bits, making for a 6-byte instruction.
Displacement addressing can be useful for referencing global variables.
The remaining addressing modes are indirect, in the sense that the address portion of the instruction tells the processor where to look to find the address. The base mode specifies that one of the 8-, 16-, or 32-bit registers contains the effective address. This is equivalent to what we have referred to as register indirect addressing.
In the base with displacement mode, the instruction includes a displacement to be added to a base register, which may be any of the general-purpose registers. Examples of uses of this mode are as follows:
• Used by a compiler to point to the start of a local variable area. For example,the base register could point to the beginning of a stack frame, which contains the local variables for the corresponding procedure.
• Used to index into an array when the element size is not 1, 2, 4, or 8 bytes and which therefore cannot be indexed using an index register. In this case, the displacement points to the beginning of the array, and the base register holds the results of a calculation to determine the offset to a specific element within
the array.
• Used to access a field of a record. The base register points to the beginning of the record, while the displacement is an offset to the field.
In the scaled index with displacement mode, the instruction includes a displacementto be added to a register, in this case called an index register. The index register may be any of the general-purpose registers except the one called ESP, which is generally used for stack processing. In calculating the effective address, the contents of the index register are multiplied by a scaling factor of 1, 2, 4, or 8, and
then added to a displacement. This mode is very convenient for indexing arrays. A scaling factor of 2 can be used for an array of 16-bit integers. A scaling factor of 4 can be used for 32-bit integers or floating-point numbers. Finally, a scaling factor of 8 can be used for an array of double-precision floating-point numbers.
The base with index and displacement mode sums the contents of the base register, the index register, and a displacement to form the effective address. Again, the base register can be any general-purpose register and the index register can be any general-purpose register except ESP. As an example, this addressing mode could be used for accessing a local array on a stack frame. This mode can also be
used to support a two-dimensional array; in this case, the displacement points to the beginning of the array, and each register handles one dimension of the array.
The based scaled index with displacement mode sums the contents of the index register multiplied by a scaling factor, the contents of the base register, and the displacement.This is useful if an array is stored in a stack frame; in this case, the array elements would be 2, 4, or 8 bytes each in length. This mode also provides efficient indexing of a two-dimensional array when the array elements are 2, 4, or 8 bytes in length.
Finally, relative addressing can be used in transfer-of-control instructions. A displacement is added to the value of the program counter, which points to the next instruction. In this case, the displacement is treated as a signed byte, word, or doubleword value, and that value either increases or decreases the address in the program counter.
13.2.B ARM Addressing Modes
Typically, a RISC machine, unlike a CISC machine, uses a simple and relatively straightforward set of addressing modes. The ARM architecture departs somewhat from this tradition by providing a relatively rich set of addressing modes. These modes are most conveniently classified with respect to the type of instruction.
LOAD/STORE ADDRESSING
• Offset: For this addressing method, indexing is not used. An offset value is added to or subtracted from the value in the base register to form the memory address. As an example Figure 13.3a illustrates this method with the assembly language instruction STRB r0, [r1, #12]. This is the store byte instruction.
In this case the base address is in register r1 and the displacement is an immediate value of decimal 12. The resulting address (base plus offset) is the location where the least significant byte from r0 is to be stored.
• Preindex: The memory address is formed in the same way as for offset addressing. The memory address is also written back to the base register. In other words, the base register value is incremented or decremented by the offset value. Figure 13.3b illustrates this method with the assembly language instruction STRB r0, [r1, #12]!. The exclamation point signifies preindexing.
• Postindex: The memory address is the base register value. An offset is added to or subtracted from the base register value and the result is written back to the base register. Figure 13.3c illustrates this method with the assembly language instruction STRB r0, [r1], #12.
Note that what ARM refers to as a base register acts as an index register for preindex and postindex addressing. The offset value can either be an immediate value stored in the instruction or it can be in another register. If the offset value is in a register, another useful feature is available: scaled register addressing. The value in the offset register is scaled by one of the shift operators: Logical Shift Left,
Logical Shift Right, Arithmetic Shift Right, Rotate Right, or Rotate Right Extended (which includes the carry bit in the rotation). The amount of the shift is specified asan immediate value in the instruction.
DATA PROCESSING INSTRUCTION ADDRESSING
Data processing instructions use either register addressing or a mixture of register and immediate addressing. For register addressing, the value in one of the register operands may be scaled usingone of the five shift operators defined in the preceding paragraph.
BRANCH INSTRUCTIONS
The only form of addressing for branch instructions is immediate addressing. The branch instruction contains a 24-bit value. For address calculation, this value is shifted left 2 bits, so that the address is on a word boundary. This the effective address range is {32 MB from the program counter.
LOAD/STORE MULTIPLE ADDRESSING
Load Multiple instructions load a subset (possibly all) of the general-purpose registers from memory. Store Multiple instructions store a subset (possibly all) of the general-purpose registers to memory. The list of registers for the load or store is specified in a 16-bit field in the instruction with each bit corresponding to one of the 16 registers. Load and Store Multiple addressing modes produce a sequential range of memory addresses. The lowest-numbered register is stored at the lowest memory address and the highest numbered register at the highest memory address. Four addressing modes are used
(Figure 13.4): increment after, increment before, decrement after,
and decrement before. A base register specifies a main memory address
where register values are stored in or loaded from in ascending
(increment) or descending (decrement) word locations. Incrementing or
decrementing starts either before or after the first memory access.
These instructions are useful for block loads or stores, stack operations, and procedure exit sequences.
For register operand mode, the operand is located in a register. For general instructions, such as data transfer, arithmetic, and logical instructions, the operand can be one of the 32-bit general registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP,EBP), one of the 16-bit general registers (AX, BX, CX, DX, SI, DI, SP, BP), or one of the 8-bit general registers (AH, BH, CH, DH, AL, BL, CL, DL). There are also some instructions that reference the segment selector registers (CS, DS, ES, SS, FS, GS).
The remaining addressing modes reference locations in memory. The memory location must be specified in terms of the segment containing the location and the offset from the beginning of the segment. In some cases, a segment is specified explicitly; in others, the segment is specified by simple rules that assign a segment by default.
In the displacement mode, the operand’s offset (the effective address of Figure13.2) is contained as part of the instruction as an 8-, 16-, or 32-bit displacement.With segmentation, all addresses in instructions refer merely to an offset in a segment. The displacement addressing mode is found on few machines
because, as mentioned earlier, it leads to long instructions. In the case of the x86,
Table 13.2 x86 Addressing Modes
LA = linear address
(X) = contents of X
SR = segment register
PC = program counter
A = contents of an address field in the instruction
R = register
B = base register
I = index register
S = scaling factor
the displacement value can be as long as 32 bits, making for a 6-byte instruction.
Displacement addressing can be useful for referencing global variables.
The remaining addressing modes are indirect, in the sense that the address portion of the instruction tells the processor where to look to find the address. The base mode specifies that one of the 8-, 16-, or 32-bit registers contains the effective address. This is equivalent to what we have referred to as register indirect addressing.
In the base with displacement mode, the instruction includes a displacement to be added to a base register, which may be any of the general-purpose registers. Examples of uses of this mode are as follows:
• Used by a compiler to point to the start of a local variable area. For example,the base register could point to the beginning of a stack frame, which contains the local variables for the corresponding procedure.
• Used to index into an array when the element size is not 1, 2, 4, or 8 bytes and which therefore cannot be indexed using an index register. In this case, the displacement points to the beginning of the array, and the base register holds the results of a calculation to determine the offset to a specific element within
the array.
• Used to access a field of a record. The base register points to the beginning of the record, while the displacement is an offset to the field.
In the scaled index with displacement mode, the instruction includes a displacementto be added to a register, in this case called an index register. The index register may be any of the general-purpose registers except the one called ESP, which is generally used for stack processing. In calculating the effective address, the contents of the index register are multiplied by a scaling factor of 1, 2, 4, or 8, and
then added to a displacement. This mode is very convenient for indexing arrays. A scaling factor of 2 can be used for an array of 16-bit integers. A scaling factor of 4 can be used for 32-bit integers or floating-point numbers. Finally, a scaling factor of 8 can be used for an array of double-precision floating-point numbers.
The base with index and displacement mode sums the contents of the base register, the index register, and a displacement to form the effective address. Again, the base register can be any general-purpose register and the index register can be any general-purpose register except ESP. As an example, this addressing mode could be used for accessing a local array on a stack frame. This mode can also be
used to support a two-dimensional array; in this case, the displacement points to the beginning of the array, and each register handles one dimension of the array.
The based scaled index with displacement mode sums the contents of the index register multiplied by a scaling factor, the contents of the base register, and the displacement.This is useful if an array is stored in a stack frame; in this case, the array elements would be 2, 4, or 8 bytes each in length. This mode also provides efficient indexing of a two-dimensional array when the array elements are 2, 4, or 8 bytes in length.
Finally, relative addressing can be used in transfer-of-control instructions. A displacement is added to the value of the program counter, which points to the next instruction. In this case, the displacement is treated as a signed byte, word, or doubleword value, and that value either increases or decreases the address in the program counter.
13.2.B ARM Addressing Modes
Typically, a RISC machine, unlike a CISC machine, uses a simple and relatively straightforward set of addressing modes. The ARM architecture departs somewhat from this tradition by providing a relatively rich set of addressing modes. These modes are most conveniently classified with respect to the type of instruction.
LOAD/STORE ADDRESSING
• Offset: For this addressing method, indexing is not used. An offset value is added to or subtracted from the value in the base register to form the memory address. As an example Figure 13.3a illustrates this method with the assembly language instruction STRB r0, [r1, #12]. This is the store byte instruction.
In this case the base address is in register r1 and the displacement is an immediate value of decimal 12. The resulting address (base plus offset) is the location where the least significant byte from r0 is to be stored.
• Preindex: The memory address is formed in the same way as for offset addressing. The memory address is also written back to the base register. In other words, the base register value is incremented or decremented by the offset value. Figure 13.3b illustrates this method with the assembly language instruction STRB r0, [r1, #12]!. The exclamation point signifies preindexing.
• Postindex: The memory address is the base register value. An offset is added to or subtracted from the base register value and the result is written back to the base register. Figure 13.3c illustrates this method with the assembly language instruction STRB r0, [r1], #12.
Note that what ARM refers to as a base register acts as an index register for preindex and postindex addressing. The offset value can either be an immediate value stored in the instruction or it can be in another register. If the offset value is in a register, another useful feature is available: scaled register addressing. The value in the offset register is scaled by one of the shift operators: Logical Shift Left,
Logical Shift Right, Arithmetic Shift Right, Rotate Right, or Rotate Right Extended (which includes the carry bit in the rotation). The amount of the shift is specified asan immediate value in the instruction.
DATA PROCESSING INSTRUCTION ADDRESSING
Data processing instructions use either register addressing or a mixture of register and immediate addressing. For register addressing, the value in one of the register operands may be scaled usingone of the five shift operators defined in the preceding paragraph.
BRANCH INSTRUCTIONS
The only form of addressing for branch instructions is immediate addressing. The branch instruction contains a 24-bit value. For address calculation, this value is shifted left 2 bits, so that the address is on a word boundary. This the effective address range is {32 MB from the program counter.
Load Multiple instructions load a subset (possibly all) of the general-purpose registers from memory. Store Multiple instructions store a subset (possibly all) of the general-purpose registers to memory. The list of registers for the load or store is specified in a 16-bit field in the instruction with each bit corresponding to one of the 16 registers. Load and Store Multiple addressing modes produce a sequential range of memory addresses. The lowest-numbered register is stored at the lowest memory address and the highest numbered register at the highest memory address. Four addressing modes are used
These instructions are useful for block loads or stores, stack operations, and procedure exit sequences.
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